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Threats evolve. Your secure hardware should too.

QCIM Engine

  • Algorithms: ML-KEM, ML-DSA, classical algorithms, and more.
  • Design priorities: Compact, agile, side-channel secure
  • Form factor: Soft IP, synthesizable RTL for your ASIC or FPGA

The QCIM Engine is synthesizable cryptographic IP for ASICs and FPGAs built on our compute-in-memory architecture. Its reprogrammable design allows multiple classical and post-quantum algorithms to share a compact hardware foundation with integrated side-channel protections.

SHA-3 / SHAKEAESML-KEMML-DSAFN-DSAHQCLMS / XMSS+ more— AVAILABLE KERNELS- - ROADMAP · SAME CORE
Design priorities

Design priorities: crypto agility, side-channel security, silicon efficiency.

01

Crypto agility

QCIM replaces the one-core-per-algorithm model with a single compute-in-memory architecture that executes versioned cryptographic kernels. Device makers now have a practical way to adapt cryptography throughout the life of their product.

02

Side-channel security

QCIM keeps sensitive operations within a controlled compute-in-memory structure designed to reduce leakage through timing, power, and electromagnetic emissions.

03

Silicon efficiency

Optimized for low power and small die area. QCIM bundles all deployed algorithms in the same IP block, holding PPA down to a single crypto-engine footprint and shifting cryptographic work off general-purpose CPUs.

04

Competitive performance

A highly parallel datapath keeps QCIM competitive with fixed-function accelerators across ML-KEM, ML-DSA, AES, and SHA-3.

Measured benchmarks available on request, supplied with test configuration, baseline, clock assumptions, and FPGA or simulation status.

Our new architecture makes all four possible. ↓

Compute-in-memory

The unique architecture behind QCIM.

Traditional computer cores move data between memory and separate, fixed-function processing blocks. QCIM instead performs cryptographic operations where intermediate data is stored, allowing multiple algorithms to share the same logic.

What compute-in-memory enables

Practical crypto agility

New and updated algorithms can use the same protected hardware foundation rather than requiring a separate accelerator and security implementation for each one.

Side-channel resistance by design

Sensitive intermediate values remain within QCIM's controlled compute-and-memory structure, reducing observable data movement and allowing protections to be applied consistently across algorithms.

Small PPA footprint

Less data movement and duplicated circuitry reduce area and power requirements.

Compute-in-memory has been a long-standing idea in the cryptographic research community. The QCIM Engine is the first time it's available in deployable commercial hardware.

Reference

Specifications.

• Available Now – FPGA IP

Architecture

  • Reprogrammable compute-in-memory cryptographic accelerator
  • Single hardware architecture for classical, post-quantum, and future cryptographic kernels
  • Highly parallel, shallow-logic datapath optimized for memory-intensive cryptography
  • 55,000-gate cryptographic core in the current benchmark configuration
  • Configurable FPGA memory backend using inferred BRAM
  • Synthesizable RTL architecture with ASIC SRAM-macro support

Host interface and integration

  • 32-bit AHB-Lite target interface
  • 256 KB accelerator address aperture
  • Memory-mapped control, program, data, and status registers
  • Kernel-completion and error interrupts
  • External fault-injection input
  • Dedicated entropy and integrity sideband
  • Single-clock accelerator integration
  • Optional power-control signals for ASIC memory macros

Integration configurations

  • Accelerator mode: QCIM core connected to an existing host CPU or SoC fabric over AHB-Lite
  • Subsystem mode: QCIM with an integrated Ibex RV32 controller, instruction and data memory, host FIFOs, firmware loader, and result mailbox
  • Reference platform: end-to-end implementation for the ChipWhisperer CW340 Luna FPGA platform

Standards and assurance targets

  • CNSA 2.0 algorithm suite (FIPS 203, FIPS 204)
  • FIPS 140-3
  • NIST Cryptographic Module Validation Program
  • Common Criteria EAL5+
  • ISO/IEC 27001-aligned development controls
  • Independent side-channel and security-laboratory testing

Hardware security features

  • Configurable hardware masking support
  • Two-share masked data interface option
  • SECDED protection for AHB address and data transport
  • Parity-protected integrity sideband
  • Integrated fault detection and reporting
  • Automatic error and zeroization path
  • Integrated deterministic random bit generator
  • External entropy interface for secure DRBG seeding
  • Sticky integrity-status reporting and software-controlled clearing
Reference

Algorithmic support.

Algorithm
Parameters and modes
Availability
Available today · 5 algorithm families
ML-KEM
ML-KEM-512
Available
ML-KEM-768
Available
ML-KEM-1024
Available
ML-DSA
ML-DSA-44
Available
ML-DSA-65
Available
ML-DSA-87
Available
AES
AES-128
Available
AES-192
Available
AES-256
Available
SHA-3
SHA3-256
Available
SHA3-384
Available
SHA3-512
Available
SHAKE
SHAKE128, SHAKE256
Available
Roadmap · 5 algorithm families
ECDSA
P-256
Roadmap
HAETAE
HAETAE-2, 3, 5
Roadmap
HQC
HQC-128, 192, 256
Roadmap
LMS / XMSS
Configurations to be announced
Roadmap
FN-DSA
FN-DSA-512, 1024
Roadmap

Evaluate QCIM Engine in your architecture.

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