QCIMby BTQ
Technology overview

QCIM Overview

Quantum-secure cryptographic IP delivering comprehensive asymmetric crypto capabilities with minimal silicon footprint for FPGA and ASIC integration.

Form factor
Soft IP
Configurations
04 + custom
FPGA IP
Available
ASIC IP
2027
What is QCIM?

Quantum Compute in Memory.

Hardware designers face a difficult challenge to support new PQC in their chips: post-quantum algorithms use more memory, cover many unfinalized standards across the world, and have almost no hardened implementations at scale.

QCIM stands for Quantum Compute in Memory. It is a new approach to secure-enclave technology that uses a new kind of crypto engine in a super area-efficient, power-efficient, and highly secure design that can be re-used across all standardized cryptographic algorithms.

It's a hardened HW block, with the ability for designers and firmware engineers to update its cryptographic suite with new authorized kernels — without redesigning a new hardware block for every new algorithm.

Figure 01

Compute happens in memory.

QCIM's near-memory logic operates on cryptographic state in-place over a wide 512-bit interface. The PIM control path orchestrates kernels; only 32-bit operands cross to the system bus.

Internal width
512+ bits
External width
32 bits (AHB)
Power profile
Sub-mW idle / scaling
QCIM IP Block DiagramInternal architecture of the QCIM IP: SRAM banks connect via a 512+ bit link to near-memory logic, which drives a memory decoder and is coordinated by PIM control logic — both then exposing 32-bit interfaces to the system AHB.SRAM Banks512+ BITSNear-Memory LogicIN-PLACE CRYPTOGRAPHIC EXECUTIONMemory DecoderPIM ControlLogic32 BITS32 BITSSYSTEM BUS · AHB
Fig 01 — QCIM IP internals
Figure 02

QCIM within a secure-element SoC.

The cryptographic accelerator integrates alongside a Secure Core, scrambled SRAM and eFLASH memories, and a hardened peripheral bus. Every memory and bus carries integrity protection; every perimeter has tamper sensing.

  • AHB / APBHardened buses with data + address masking and integrity codes
  • MemoriesSRAM scrambled + integrity-checked. eFLASH SSP-encrypted.
  • TamperActive shield over SRAM. Glitch / temp / laser / frequency sensors.
  • EntropyvPUF Elite combines PUF + TRNG (AIS-31 / SP800-90B compliant).
QCIM Chip Block DiagramArchitecture of a secure-element SoC with the QCIM cryptographic accelerator integrated alongside the Secure Core, scrambled SRAM and eFLASH memories, peripheral bus, and tamper-resistance subsystems.AHB LITE · DATA/ADDRESS MASKING · INTEGRITYAPB · MASKING · INTEGRITYBRIDGESecure CoreWITH MPUSRAM38 KBQCIMCRYPTO-IN-MEMORYSRAM64 KBSCRAMBLED + INTEGRITYSPIROM64 KBeFLASH512 KBSCRAMBLED + ENCRYPTED + INTEGRITYCACHEAnalog IPLDO · BGR · POR · BOD · OSCActive shieldTamper sensorsGLITCH · TEMP · LASER · FREQOTPWITH INTEGRITYIOMUXLife cycle ctrlGPIO7816I2CClk / Rst ctrlTimersvPUF ElitePUF + TRNG
Fig 02 — QCIM in a secure-element SoC
Two products, one architecture

The crypto engine. The root-of-trust. Same core.

Crypto Engine

QCIM Crypto Engine

The all-in-one asymmetric cryptographic block. Built on Processing-in-Memory (PIM) architecture, QCIM Crypto Engine handles RSA, ECC, and post-quantum algorithms without dedicated accelerator blocks. A single unified engine that maximizes memory and compute efficiency.

  • · PIM architecture for memory-efficient crypto operations
  • · Integrated secure memory for keys and intermediate values
  • · Firmware-updateable algorithms for crypto agility
  • · Flexible algorithm kernel memory with configurable sizes
Figure 01 above — IP block diagram↑
Root of Trust

QCIM Root-of-Trust

Complete Hardware Root-of-Trust integrating the QCIM Crypto Engine with comprehensive security mechanisms. Provides secure boot, attestation, key management, and hardened protection against physical and logical attacks.

  • · Secure boot with chain-of-trust verification
  • · Remote attestation and device identity services
  • · OTP key storage and secure key derivation
  • · Anti-tamper detection, response, and key zeroization
  • · Zero-touch provisioning and binding support
Figure 02 above — secure-element SoC↑
Why crypto agility

Why crypto agility matters for hardware roots-of-trust.

The RoT challenge

Hardware Roots-of-Trust must handle diverse cryptographic requirements across their lifetime: different global standards (NIST, BSI, ETSI), evolving protocols (TLS, IPsec, V2X), PKI operations, attestation, and secure boot. Traditional fixed-function crypto blocks require costly silicon redesigns and re-certification when any standard evolves.

Worse, re-certification can take 12-18 months and cost millions — making algorithm updates practically impossible for deployed systems. Products with 10+ year lifecycles are locked into obsolete cryptography.

QCIM's solution

QCIM's firmware-updateable crypto agility means your silicon doesn't change when algorithms do. The crypto-agile architecture maintains certification across algorithm updates because the hardware security boundaries remain constant — only the firmware algorithms evolve.

This enables: zero-touch provisioning workflows that adapt to new protocols, binding mechanisms that support emerging standards, attestation with larger payloads for PQC, and long-lived secure enclaves that remain compliant for 15+ years without hardware respins.

Growing secure-enclave demands

Modern secure enclaves face unprecedented memory and compute pressure: larger attestation payloads (PQC signatures are 10× bigger), zero-touch provisioning from the secure enclave on boot, expanded SRAM and mailboxes for PQC key material, and simultaneous protocol support.

QCIM's PIM architecture maximizes available resources for these trends while maintaining comprehensive cryptographic capabilities. You get more memory and compute for your application while hardened crypto remains available.

Availability

FPGA IP today. ASIC IP on roadmap.

Core capabilities
Capability matrix · NDA gates the full datasheet

Every feature, every configuration, every form factor.

Certification packages available upon request: Current certification status, roadmap timelines, evidence packages, compliance matrices, and guidance for customer-specific certification requirements. QCIM's crypto agility prevents re-certification when algorithm standards evolve.

FeatureQCIM CoreQCIM DataspeedQCIM RoTQCIM Safety RoTCustom Implementation
FPGAASICFPGAASICFPGAASICFPGAASICFPGAASIC
Existing Asymmetric Cryptography Support
Symmetric Cryptography Support
Post-Quantum Cryptography Support
Legacy Secure Boot Support
PQC Secure Boot Support
Secure Key Management
Key Derivation
PUF Included
DPA Secure Algorithms
DPA Secure Hardware
Anti-Tamper Mechanisms
OTP Key Management
Memory ECC
Multiple RoT Support
Secure Debug
FIPS 140-3
ISO 26262
CC EAL 5+
PSA Certified
SESIP
IEC 62443

· Capability marks pending datasheet finalization. Detailed support matrix available under NDA.

Resource calculator

Estimate FPGA resources for your design.

The Custom Implementation page includes an interactive calculator — pick your algorithm, throughput tier, and security level, get LUT / latency / memory estimates.

Open the calculator→Algorithm · Throughput · Security level
Performance

Algorithms, throughput, resources.

Algorithm support
RSA
2048-4096 bit
ECC
P-256, P-384, P-521
PQC
ML-DSA, ML-KEM
Throughput
RSA-2048
200+ ops/sec
ECDSA P-256
500+ ops/sec
AES-256
50+ MB/s
Resources
Area
Configurable
Power
Low to high
FPGA
Xilinx · Intel

· Detailed specifications available upon request.

Integration

FPGA today. ASIC on the path.

FPGA flow

  1. 01Drop-in IP core with standard bus interfaces (AXI, APB)
  2. 02Pre-configured synthesis and timing constraints
  3. 03Comprehensive software drivers and API documentation

ASIC flow

  1. 01Synthesizable RTL with DFT and scan insertion support
  2. 02Technology-agnostic design portable across foundries
  3. 03Integration support and validation test suites

Get started with QCIM.

Request detailed technical specifications, evaluation licenses, or schedule a consultation with our engineering team.

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