Configuration overview
Three things QCIM Core does no other accelerator does.
01Smallest PQC engine.
Minimal LUT and area utilization, enabling PQC deployment in existing chips.
Anchored at <5K LUTs, QCIM Core is the most compact NIST-aligned post-quantum accelerator commercially available — small enough to drop into existing secure-element silicon without re-floorplanning.
< 5KLUTs
02Ultra-low power.
Sub-milliwatt operation for battery-powered IoT and energy-constrained edge devices.
Designed for 15+ year field lifetimes. Idle draw is sub-mW; active operation scales with workload. Works inside the power envelope of battery-driven sensors and industrial controllers.
sub-mWIdle profile
03PQC-ready security.
Mandated NIST post-quantum algorithms plus essential symmetric crypto in minimal footprint.
ML-KEM and ML-DSA (NIST FIPS 203 / 204) cover the required PQC envelope. AES and SHA-3 round out the symmetric stack — all in a single soft IP block.
ML-KEM · ML-DSANIST PQC
Key features
The full envelope, in one block.
Algorithm Support- ML-KEM (NIST PQC KEM)
- ML-DSA (NIST PQC Signatures)
- AES-128 / 256
- SHA-3
Key Advantages- Drop-in PQC for existing chips
- Smallest die area for PQC
- Ultra-low power consumption
- Battery-friendly profile
Resource Utilization- <5K LUTs (minimal)
- Sub-milliwatt idle operation
- <50 mW active (target)
- Smallest die area for PQC
Integration- AXI / APB bus interfaces
- FPGA synthesis scripts
- Reference C drivers
- Validation test suite
Performance characteristics
Validated on Xilinx Ultrascale+.
Throughput- ML-DSA Sign
- 100+ ops/sec
- ML-KEM Encaps
- 150+ ops/sec
- AES-256
- 50+ MB/s
Resource usage- LUTs
- ~5,000
- BRAM
- 64 KB
- Power
- <50 mW (active)
Latency- RSA-2048
- ~5 ms
- ECDSA P-256
- ~2 ms
- Boot time
- <100 ms
· Performance measured on Xilinx Ultrascale+ at 100 MHz. Detailed benchmarks available under NDA.