Line-speed crypto. Post-quantum signatures. One package.

Line-speed AES.

Deeply pipelined symmetric stack targeting 100G+ Ethernet line rate.

An AES engine stack built for sustained throughput — pipelined deeply enough to absorb line-rate traffic at 100G+ with minimal added latency, sized for switch and NIC budgets rather than general-purpose offload.

Asymmetric crypto core.

QCIM PIM core handles ML-KEM, ML-DSA, and legacy asymmetric.

The same QCIM compute-in-memory core that anchors the rest of the family executes ML-KEM, ML-DSA, RSA, and ECC — so post-quantum key exchange and signatures share a path with the symmetric pipeline rather than bolting on a second accelerator.

Data-center optimized.

Concurrent symmetric and asymmetric crypto in a hyperscale footprint.

Sized for the constraints that govern hyperscale infrastructure and high-throughput security appliances: predictable latency, concurrent symmetric and asymmetric workloads, and an area envelope small enough to land beside the data plane.